Logic Design and Verification Using SystemVerilog (Revised)

SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: -students currently in an introductory logic design course that also teaches SystemVerilog, -designers who want to update their skills from Verilog or VHDL, and -students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design - these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book's topics.The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning.Solutions to problems at the end of chapters, and text copies of the SystemVerilog examples are available from the author as described in the Preface.

Author: Donald Thomas
Publisher: Createspace Independent Publishing Platform
Published: 03/01/2016
Pages: 336
Binding Type: Paperback
Weight: 1.32lbs
Size: 9.69h x 7.44w x 0.70d
ISBN13: 9781523364022
ISBN10: 1523364025
BISAC Categories:
- Computers | Logic Design

About the Author
Donald Thomas is Professor Emeritus of Electrical and Computer Engineering at Carnegie Mellon University where he has taught logic design, RT-level design, design languages (Verilog and SystemVerilog), verification, and computer-aided design algorithms for the design of integrated circuits and systems.

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